PCB Design Rules

An additional question came up here: Could you add the BGA-Pad to BGA-Pad distance? And also the minimum BGA-Pad size?

PS: Thank you so much for adding the t, u and v values!

Hi @andreas_eet,

welcome to the community and thank you for the hint! The distance (t, u, v) is now listed above!

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Hi @CommanderLake,

welcome to the community!

“Edit: I realise now what this means, the filled in area is where the copper is.”

Exactly!

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Hi @andreas-eet,

thanks for this feedback, we will try to include this in our article, too!

Thank you!

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@christina , your posts states

Please also note that these rules are the bare minimum that we support. If you can leave some safety margins in your design, the PCBs will be more likely to work the way you intended them to.

is this mostly intended for traces and clearances or also for via sizes?
I am designing a PCB and using the smallest possible vias would be really beneficial (0.6/0.2)
is it save to use lots of these vias (around 30) or would it be better to go for (0.7/0.3)?

Hi @miloz,

welcome to the community!

In principle, this statement also refers to the dimension of vias. But if small vias (0.6/0.2) help you to realise your specific layout and thus bring you added value, then there is nothing to say against using them!

Best regards,
Manuel

Hi,
i stumbled across the same thing and still have some questions.
What polarity should be used for the outer layers?

I should be able to see the used polarity in KICAD, since copper traces and planes get displayed normal (positive) or inverted (negative) right?

Thanks in advance!

Nothing has to be negative.

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Is there a reason why the the eagle design rules on github are quite different from those above?
Which one should I use?

Hi @etik,

Welcome to the community!
I guess you mean the clearance/spacing values for simple? We included a little security margin and set them to 175 µm – if you need to, you can reduce those values to 150 µm in the .dru-file according to the table above.

In general, we try to keep the design rule files up to date. However, in case of doubt, the values listed above apply.

I would like to mention again that these values are minimum values. If your layout allows it, it does certainly make sense to design widths and distances with some safety margin.

Best regards,
Manuel

A post was merged into an existing topic: Plated and Non-Plated Slots and Cutouts

Hallo,

I am trying to route the LP8550, which have DSBGA 25 Footprint with 0.5 mm Pitch. Using this design-rules (4 Layer complex) it is impossible to route it.

If I kept the drill size 0.2 mm and tried to achieve outer-diameter from 0.35 mm (see Photo), is it possible to manufacture it?

One more question, are Ball-Pads supported?

I think that I and all Others will appreciate an article just about BGAs :smiley:.

Best Regards
Asmandar

Hi @kompass ,

Welcome to the community!

If I kept the drill size 0.2 mm and tried to achieve outer-diameter from 0.35 mm (see Photo), is it possible to manufacture it?

For BGAs with a pitch of 0.5 mm, we are at the limit of our technical capabilities.
Your suggestion to reduce the pad diameter to 0.35 mm - as I understand you - is not sufficient for a safe through-hole plating. Another problem with a 0.5 mm pitch is the minimum drill spacing (please see also here)

One more question, are Ball-Pads supported?

Do you mean via-in-pad? In principle, you can use via-in-pads in your layout and have them manufactured by us. However, please note that we do not fill the borehole. This allows solder to flow through the hole during assembly. When using our assembly service, via-in-pads are therefore not permitted.

I think that I and all Others will appreciate an article just about BGAs

Thanks for the feedback - it’s noted! :wink:

Best regards,
Manuel

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Hello,

do i understand it correctly, that the minimum annular ring of a via has to be 0,2mm?

I would like to use vias with 0,2mm hole and 0,1mm ring. Would that be possible?

Would this match your rules?:

And would it be possible to do it like this?:

Thank you

edit:
Wenn I upload the file (like shown in the second picture) to your service, no error is displayed.

Hi @crally-crally-de ,

welcome to the community!

do i understand it correctly, that the minimum annular ring of a via has to be 0,2mm?

Correct!

I would like to use vias with 0,2mm hole and 0,1mm ring. Would that be possible?

As these vias do not comply with our design rules, they are manufactured at your own risk.

Would this match your rules?

The vias (0.2 mm drill diam, 0.6 mm pad diameter) are correctly dimensioned. Please note that sufficient distance is maintained between Via-Pad and other copper structures!

Wenn I upload the file (like shown in the second picture) to your service, no error is displayed.

That is correct. It is your responsibility to upload a compliant design!

Best regards,
Manuel

What happens when a outline crosses a pad like when Kicad says “Line on F.Silkscreen”.
Is the line then printed on the pad or not?

Hi @HansP ,

Welcome to the community!

When processing your data, we remove the silkscreen print on and in the immediate vicinity of openings in the soldermask (= most pads). You can see the result in our Board Viewer - only the silkscreen that is displayed there will be printed.

Best regards,
Manuel

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Thank you. This will help to not modify all the footprints :slight_smile:

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I assume that oval holes are complex, but I thought I’d ask for clarity.
Thanks!

Hi @Scriven ,

Right, oval holes lead to a complex rating of the board.

Cheers,
Manuel

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